Volatile and non-volatile memory arrays can have yield degradations due to problems occurring during manufacture of the memory array as well as during use of the memory array in the field. To improve manufacture-related yield in some memory arrays, the memory array can be tested at the factory, and redundancy circuits in the memory device can replace faulty blocks of memory (e.g., faulty bits, bytes, columns, rows, or sub-arrays) prior to shipment. To improve field-related yield, parity checking or error-correcting code (“ECC”) algorithms can be used. The use of these algorithms is particularly important for once-programmable non-volatile memories (e.g., PROM) because individual memory cells cannot be programmed, tested, and then erased prior to shipment. Commonly-used ECC algorithms can correct single-bit errors and detect (but not correct) multi-bit errors. More-powerful ECC algorithms can be used to correct multi-bit errors, but the overhead of the circuitry and extra syndrome bits associated with those more-powerful algorithms may be undesirable.